Did you hear the joke about the 128 bit processor? Let me offer some factual corrections to an article which appeared a couple of days ago in the Korea Herald and which has fueled speculation…
This is an incredibly exciting time for the ARM ecosystem, with leading solutions from ARM partners taking computing to the next level. Over the past month, beginning at the ARM TechCon event in Santa Clara and continuing worldwide at our ARM Technical Symposia, we have publicly presented the future of ARM technologies to over 7000 engineers and counting. Those engineers have seen the facts:
News reports have suggested that ARM is developing 128-bit processor technology: this is not true. 64-bit processors are capable of supporting the needs of the computing industry now and for many years to come. There are absolutely no plans underway for 128 bit ARM-based chips because they simply aren’t needed. Rumors to the contrary are simply incorrect.
Furthermore, comments attributed to any ARM executive including my colleague Antonio Viana that allegedly discuss any specific partner’s chip plans for the future or 128 bit development are inaccurate: no such comments have been made.
The ARM partnership is built around diversity of solutions, and ARM works diligently to assure our partners can announce their products at a time of their choosing, and showing their unique technical differentiation and value add. As a result, we absolutely do not disclose our partners product plans but defer to partners to make their own statements. The result is a vibrant marketplace of innovative solutions that serve a range of end application needs, which I find incredibly exciting.
Yes, at present it would probably be silly to have an 128-bit address path. Perhaps it would also be silly to have a 128-bit data path.
But I think having 128-bit registers for data processing (integer and float) might be interesting, though.
I believe that a 64/128-bit processor might be the next thing we'll see. Perhaps the register width will be increased further - maybe to 256 bits, before we even see a 128-bit data- or address-path.
One might (over-)simplify the meaning of the three:
The current NEON can already achieve128 bits registers by viewing as 16 registers. But double the number of 128 bits registers in next generation neon would be an attractive idea :)
Here's a review paper that (partly?) captures the current interest in higher-than-double precision arithmetic.
I spoke with Bailey recently and he was saying it'd be great to see h/w support for double double in HPC