ARM® CoreLink™ System IP performance analysis with the Cadence Interconnect Workbench

-       Reduce time to market and improve performance of your ARM-based SoC

Today’s smartphone design complexity is addressed with ARM® CoreLink™ system intellectual property (IP) to manage the connections of the processing subsystem, memory subsystem, and the array of peripherals. The ARM CoreLink 400 system IP provides the highest possible performance while meeting the mobile thermal and power profile. The system IP is configurable to support the wide variety of peripheral combinations for the smartphone market. To harness the power of this solution and validate that performance requirements are met, one must analyze the configured IP under a variety of system use cases..

The Cadence Interconnect Workbench is a performance analysis and functional verification solution for ARM CoreLink system IP system-on-chip (SoC) devices. The Interconnect Workbench performs cycle-accurate measurement of transaction latency and bandwidth as tracked from master to slaves on cascaded interconnects containing the CCI-400™ and NIC-400™. IP-specific traffic models automatically create a wide spectrum of system use cases where interesting traffic congestion occurs. The performance analyzer enables easy filtering and identification of outlier transactions, and tracks the precise location of relevant debugging information.

The solution enables teams to rapidly conduct performance analysis experiments that previously required weeks or months to construct by hand. Users can explore multiple configurations of an interconnect to choose the most optimal architecture. In addition, the Interconnect Workbench provides interactive debugging capabilities to aid in determining the cause of particular transaction delays. Finally, the Interconnect Workbench automatically generates a Unified Verification Methodology (UVM) testbench with the Cadence Interconnect Validator and AMBA® Verification IP (VIP), as well as a test suite to verify master-slave functionality of the interconnect.

By examining different implementation options for the ARM CoreLink 400 series system IP and running simulations for these different implementations against different use-cases, users can build a clearer picture of the impact these design decisions will make to their system’s performance. Tradeoffs can be made to find the optimum implementation options and QoS configuration for given system use cases defined by a collection of traffic profiles. Performance issues can be identified early in the project, saving weeks or months that might have been expended just before tapeout.